14 lines
271 B
Systemverilog
14 lines
271 B
Systemverilog
`timescale 1ps/1ps
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/* verilator lint_off DECLFILENAME */
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/* verilator lint_off MULTITOP */
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/* verilator lint_off STMTDLY */
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/* verilator lint_off INFINITELOOP */
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/* verilator lint_off INITIALDLY */
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module testbench;
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initial begin
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$finish;
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end
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endmodule
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