Remove clock from testbench input
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@@ -1,58 +1,43 @@
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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#include "V@TOPMODULE@.h"
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#include <cstdint>
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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#define DUMPFILE "@WORKDIR@/@TOPMODULE@.vcd"
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#define CLOCK_HALF_PERIOD 5000
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int main(int argc, char **argv)
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{
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VerilatedContext *ctx = new VerilatedContext;
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ctx->commandArgs(argc, argv);
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int main(int argc, char** argv, char**) {
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// Setup context, defaults, and parse command line
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Verilated::debug(0);
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const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
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contextp->traceEverOn(true);
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contextp->commandArgs(argc, argv);
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/* Create model instance */
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V@TOPMODULE@ *top = new V@TOPMODULE@(ctx);
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// Construct the Verilated model, from Vtop.h generated from Verilating
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const std::unique_ptr<V@TOPMODULE@> topp{new V@TOPMODULE@{contextp.get()}};
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#if (VM_TRACE == 1)
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VerilatedVcdC *vcd = new VerilatedVcdC;
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ctx->traceEverOn(true);
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top->trace(vcd, 99);
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topp->trace(vcd, 99);
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vcd->open(DUMPFILE);
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#endif
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top->clock = 0;
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/* ---- Evaluation loop ---- */
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for (;;) {
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/* Eval */
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top->eval();
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/* Trace steady-state values */
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#if (VM_TRACE == 1)
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if (vcd) vcd->dump(ctx->time());
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#endif
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/* Break exactly after calling $finish */
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if (ctx->gotFinish()) break;
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/* Clock event */
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ctx->timeInc(CLOCK_HALF_PERIOD);
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top->clock = top->clock ? 0 : 1;
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// Simulate until $finish
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while (!contextp->gotFinish()) {
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// Evaluate model
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topp->eval();
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vcd->dump(contextp->time());
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// Advance time
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if (!topp->eventsPending()) break;
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contextp->time(topp->nextTimeSlot());
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}
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top->final();
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printf("[%lu] Stop simulation\n", ctx->time());
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#if (VM_TRACE == 1)
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if (vcd) {
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vcd->close();
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delete vcd;
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if (!contextp->gotFinish()) {
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VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n"););
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}
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#endif
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delete top;
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delete ctx;
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// Execute 'final' processes
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topp->final();
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// Print statistical summary report
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contextp->statsPrintSummary();
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vcd->close();
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return 0;
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}
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