Remove clock from testbench input

_web_server/server/top_iverilog.sv

@@ -1,9 +1,8 @@
 `timescale 1ps/1ps
 
 module __@TOPMODULE@__;
-    logic clock = 1'b0;
-    initial forever #(5ns) clock = ~clock;
-    @TOPMODULE@ @TOPMODULE@ (clock);
+    @TOPMODULE@ @TOPMODULE@ ();
+
     initial begin
         $dumpfile("@WORKDIR@/@TOPMODULE@.vcd");
         $dumpvars(1, @TOPMODULE@);