np/verilog-playground
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Remove clock from testbench input

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This commit is contained in:
Nikolay Puzanov
2024-04-14 16:08:20 +03:00
parent 1e0bfb58cf
commit b84ec9a1c5
3 changed files with 41 additions and 53 deletions
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18
_web_server/server/playground-server.scm
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@@ -33,7 +33,7 @@
(define IVERILOG-EXE "iverilog")
(define VVP-EXE "vvp")
(define VERILATR-EXE "verilator")
(define VERILATOR-EXE "verilator")
(define URI-IVERILOG "iverilog")
(define URI-VERILATOR "verilator")
@@ -49,9 +49,14 @@
(define DEFAULT-CODE
(string-append
"`timescale 1ps/1ps\n\n"
(format "module ~a (input clock);\n" TOP-MODULE)
;; (format "module ~a (input clock);\n" TOP-MODULE)
(format "module ~a;\n" TOP-MODULE)
" logic clock = 1'b0;\n"
" initial forever #(5ns) clock = ~clock;\n"
"\n"
" initial begin\n"
" $display(\"Hello world!\");\n"
" repeat(10) @(posedge clock);\n"
" $finish();\n"
" end\n"
"endmodule\n"))
@@ -566,8 +571,7 @@
(with-output-to-file command-file
(lambda ()
(println "+define+TESTBENCH")
(println "-CFLAGS -fcoroutines")
(println "-DTESTBENCH")
(println "--timescale 1ps/1ps")
(println "--top-module ~a" top)
(println "--Mdir ~a" (path+ work-dir top))
@@ -580,7 +584,7 @@
(println "--build")
(println "-sv")
(println "-Wno-WIDTH")
(println "+1800-2017ext+sv")
(println "+1800-2023ext+sv")
(println "--timing")
(println "--trace")
(println "--trace-structs")
@@ -650,7 +654,7 @@
(let* ((command-file (path+ work-dir (format "~a.vc" top)))
(vcd-file (path+ work-dir (format "~a.vcd" top)))
(cmds `(,(format "~a -f ~a"
(wrap-exe VERILATR-EXE verilator-wrap)
(wrap-exe VERILATOR-EXE verilator-wrap)
command-file)
,(wrap-exe (path+ work-dir (format "~a/~a" top top))
verilator-sim-wrap))))
@@ -818,7 +822,7 @@
,(format "Icarus: ~a"
(app-version (wrap-exe IVERILOG-EXE iverilog-wrap) "-V"))
,(format "Verilator: ~a"
(app-version (wrap-exe VERILATR-EXE verilator-wrap)))
(app-version (wrap-exe VERILATOR-EXE verilator-wrap)))
""
"Rules:"
"0. Don't fool around ;)"