Add Verilator support

This commit is contained in:
Nikolay Puzanov
2022-12-03 18:36:50 +03:00
parent f61bb7b980
commit 058191de55
7 changed files with 295 additions and 140 deletions

View File

@@ -0,0 +1,11 @@
`timescale 1ps/1ps
module __@TOPMODULE@__;
logic clock = 1'b0;
initial forever #(5ns) clock = ~clock;
@TOPMODULE@ @TOPMODULE@ (clock);
initial begin
$dumpfile("@WORKDIR@/@TOPMODULE@.vcd");
$dumpvars(0, @TOPMODULE@);
end
endmodule