_web_server/server/top_iverilog.sv

`timescale 1ps/1ps

module __@TOPMODULE@__;
    @TOPMODULE@ @TOPMODULE@ ();

    initial begin
        $dumpfile("@WORKDIR@/@TOPMODULE@.vcd");
        $dumpvars(1, @TOPMODULE@);
        $dumplimit(100000);
    end
endmodule
Add Verilator support 2022-12-03 18:36:50 +03:00			`timescale 1ps/1ps

			`module __@TOPMODULE@__;`
Remove clock from testbench input 2024-04-14 16:08:20 +03:00			`@TOPMODULE@ @TOPMODULE@ ();`

Add Verilator support 2022-12-03 18:36:50 +03:00			`initial begin`
			`$dumpfile("@WORKDIR@/@TOPMODULE@.vcd");`
Enable trace of structs 2022-12-13 11:49:15 +03:00			`$dumpvars(1, @TOPMODULE@);`
Limit dump file size for Icarus Verilog 2022-12-03 23:53:03 +03:00			`$dumplimit(100000);`
Add Verilator support 2022-12-03 18:36:50 +03:00			`end`
			`endmodule`