17 lines
277 B
Systemverilog
17 lines
277 B
Systemverilog
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`timescale 1ps/1ps
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module top
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(input wire clock,
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input wire reset);
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initial begin
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for (int n = 0; n < 10; n += 1) begin
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$display("R@%0t: %0b\n", $time, reset);
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@(posedge clock);
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end
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$finish;
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end
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endmodule // top
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