verilog-playground/_template_iverilog/testbench.sv

`timescale 1ps/1ps

/* verilator lint_off DECLFILENAME */
/* verilator lint_off MULTITOP */
/* verilator lint_off STMTDLY */
/* verilator lint_off INFINITELOOP */
/* verilator lint_off INITIALDLY */

module testbench;
    initial begin
        $finish;
    end

`ifdef DUMP
    initial begin
        $dumpfile("testbench.fst");
        $dumpvars(0, testbench);
    end
`endif
endmodule