Initial commit
This commit is contained in:
Nikolay Puzanov
239
source/hsl2rgb.sv
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239
source/hsl2rgb.sv
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`timescale 1ns/100ps
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`default_nettype none
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/**
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* HSL to RGB translation.
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*
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* H, S, L = [0..1)
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*
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* Q = | L < 0.5 ? L + L*S
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* | L >= 0.5 ? L + S - L*S
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*
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* P = 2 * L - Q
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*
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* TR = H < 2/3 ? H + 1/3 : 1/3 - (1 - H)
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* TG = H
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* TB = H >= 1/3 ? H - 1/3 : 1 - H
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*
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* COLORX = | TX < 1/6 ? P + ((Q - P) * 6 * TX)
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* | 1/6 <= TX < 1/2 ? Q
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* | 1/2 <= TX < 2/3 ? P + ((Q - P) * (2/3 - TX) * 6)
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* | else : P
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*/
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/*
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* Datapath:
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*
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* if l < [1/2]
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* then: lls = l + (l * s)
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* else: lls = l - (l * s)
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*
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* m1h = ~(h - 1)
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*
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* tr =
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* if h < [2/3]
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* then: h + [1/3]
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* else: [1/3] - m1h
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*
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* tg = h
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*
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* tb =
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* if h >= [1/3]
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* then: h - [1/3]
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* else: m1h
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*
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* q =
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* if l < [1/2]
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* then: lls
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* else: lls + s
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*
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* p = l * 2 - q
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* qp = (q - l) * 2
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*
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* r =
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* p + 6 * qp * tr
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* p + 6 * qp * ([2/3] - tr)
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*
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* g =
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* p + 6 * qp * tg
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* p + 6 * qp * ([2/3] - tg)
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*
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* b =
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* p + 6 * qp * tb
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* p + 6 * qp * ([2/3] - tb)
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*/
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module hsl2rgb
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(input wire clock,
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input wire reset,
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input wire [7:0] h,
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input wire [7:0] s,
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input wire [7:0] l,
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input wire ready_i,
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output reg [7:0] r,
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output reg [7:0] g,
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output reg [7:0] b,
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output wire valid_o);
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`define C1_6 43
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`define C1_3 85
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`define C1_2 128
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`define C2_3 171
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`define C1_1 256
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localparam STAGES = 5;
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logic [STAGES-1:0] valid;
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assign valid_o = valid[STAGES-1];
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always_ff @ (posedge clock, posedge reset)
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if (reset)
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valid <= '0;
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else
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valid <= { valid[STAGES-2:0], ready_i };
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/* ---------------- Stage 1 ---------------- */
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logic [8:0] lls; // lls = l0 ± (l0 * s0)
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logic ls_sub;
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/* verilator lint_off UNUSED */
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logic [31:0] mac_lls_o;
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/* verilator lint_on UNUSED */
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assign lls = {mac_lls_o[16:8]};
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assign ls_sub = l < `C1_2 ? 1'b0 : 1'b1;
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ice40_mac16x16 mac_lls
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(.clock, .reset,
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.a({8'b0, l}),
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.b({8'b0, s}),
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.s({16'b0, l, 8'b0}),
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.sub(ls_sub),
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.y(mac_lls_o));
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/* propagate to next stage */
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logic [7:0] h1, s1, l1;
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always_ff @ (posedge clock) begin
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h1 <= h;
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s1 <= s;
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l1 <= l;
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end
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/* ---------------- stage 2 ---------------- */
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logic [8:0] q_pre;
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logic [7:0] q;
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logic [7:0] minus1h; // minus1h = 256 - h = ~(h - 1)
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always_ff @ (posedge clock) begin
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q_pre <= l1 < `C1_2 ? lls : lls + s1;
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minus1h <= ~(h1 - 1);
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end
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assign q = q_pre[8] ? 8'hff : q_pre[7:0];
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/* propagate to next stage */
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logic [7:0] h2, l2;
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always_ff @ (posedge clock) begin
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h2 <= h1;
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l2 <= l1;
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end
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/* ---------------- stage 3 ---------------- */
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logic [7:0] tr, tg, tb;
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logic [8:0] p_pre;
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logic [7:0] p; // p = l * 2 - q
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logic [7:0] qp; // qp = q - p
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always_ff @ (posedge clock) begin
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tr <= h2 < 8'(`C2_3) ? h2 + 8'(`C1_3) : 8'(`C1_3) - minus1h;
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tg <= h2;
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tb <= h2 >= 8'(`C1_3) ? h2 - 8'(`C1_3) : minus1h;
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p_pre <= (9'(l2) << 1) - q;
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qp <= 8'((q - l2) << 1);
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end
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assign p = p_pre[8] ? 8'hff : p_pre[7:0];
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/* propagate to next stage */
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logic [7:0] q3;
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always_ff @ (posedge clock)
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q3 <= q;
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/* ---------------- stage 4 ---------------- */
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logic [7:0] trx, tgx, tbx;
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logic [10:0] qp6;
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/* verilator lint_off UNUSED */
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logic [31:0] mac_r_o;
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logic [31:0] mac_g_o;
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logic [31:0] mac_b_o;
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/* verilator lint_on UNUSED */
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assign qp6 = (11'(qp) << 1) + (11'(qp) << 2);
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assign trx = (tr < `C1_6) ? tr : `C2_3 - tr;
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assign tgx = (tg < `C1_6) ? tg : `C2_3 - tg;
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assign tbx = (tb < `C1_6) ? tb : `C2_3 - tb;
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ice40_mac16x16 mac_r
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(.clock, .reset,
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.a({5'b0, qp6}),
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.b({8'b0, trx}),
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.s({16'b0, p, 8'b0}),
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.sub(1'b0),
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.y(mac_r_o));
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ice40_mac16x16 mac_g
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(.clock, .reset,
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.a({5'b0, qp6}),
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.b({8'b0, tgx}),
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.s({16'b0, p, 8'b0}),
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.sub(1'b0),
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.y(mac_g_o));
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ice40_mac16x16 mac_b
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(.clock, .reset,
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.a({5'b0, qp6}),
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.b({8'b0, tbx}),
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.s({16'b0, p, 8'b0}),
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.sub(1'b0),
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.y(mac_b_o));
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/* propagate to next stage */
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logic [7:0] tr4, tg4, tb4;
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logic [7:0] p4;
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logic [7:0] q4;
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always_ff @ (posedge clock) begin
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tr4 <= tr;
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tg4 <= tg;
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tb4 <= tb;
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p4 <= p;
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q4 <= q3;
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end
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/* ---------------- stage 5 ---------------- */
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always_ff @ (posedge clock) begin
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if (tr4 < `C1_6) r <= mac_r_o[16] ? 8'hff : mac_r_o[15:8];
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else if (tr4 < `C1_2) r <= q4;
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else if (tr4 < `C2_3) r <= mac_r_o[16] ? 8'hff : mac_r_o[15:8];
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else r <= p4;
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end
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always_ff @ (posedge clock) begin
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if (tg4 < `C1_6) g <= mac_g_o[16] ? 8'hff : mac_g_o[15:8];
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else if (tg4 < `C1_2) g <= q4;
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else if (tg4 < `C2_3) g <= mac_g_o[16] ? 8'hff : mac_g_o[15:8];
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else g <= p4;
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end
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always_ff @ (posedge clock) begin
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if (tb4 < `C1_6) b <= mac_b_o[16] ? 8'hff : mac_b_o[15:8];
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else if (tb4 < `C1_2) b <= q4;
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else if (tb4 < `C2_3) b <= mac_b_o[16] ? 8'hff : mac_b_o[15:8];
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else b <= p4;
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end
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endmodule // hsl2rgb
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