Add XSIM

2023-06-13 16:35:18 +03:00
parent 68a2501686
commit a3815caa0a
6 changed files with 31 additions and 0 deletions
--- a/test-xsim/top.sv
+++ b/test-xsim/top.sv
@@ -0,0 +1,7 @@
+`timescale 1ps/1ps
+
+module top;
+    logic clock = 1'b0;
+    initial forever #(10ns/2) clock = ~clock;
+    testbench testbench (clock);
+endmodule