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Add VCS and Xcelium run time. Fix RTL for VCS to work correctly

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Nikolay Puzanov
2023-06-21 11:27:48 +03:00
parent 519410e392
commit 31ac4a8d46
6 changed files with 51 additions and 10 deletions
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test-vcs/.dir-locals.el Normal file
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((verilog-mode . ((flycheck-verilator-include-path . ("../source")))))