Change benchmark to calc MD5 on 1024 softcores
This commit is contained in:
Nikolay Puzanov
226
source/md5calculator.sv
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226
source/md5calculator.sv
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`timescale 1ps/1ps
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module md5calculator
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(input clock,
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input reset,
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output done,
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// input [31:0] data_in,
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output [127:0] md5);
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parameter MEM_ADDR_WIDTH = 16;
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parameter ROM_ADDR_WIDTH = 16;
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/* verilator lint_off UNUSED */
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logic cpu_mem_valid;
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logic cpu_mem_instr;
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logic cpu_mem_ready;
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logic [31:0] cpu_mem_addr;
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logic [31:0] cpu_mem_wdata;
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logic [ 3:0] cpu_mem_wstrb;
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logic [31:0] cpu_mem_rdata;
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// Look-Ahead Interface
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logic cpu_mem_la_read;
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logic cpu_mem_la_write;
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logic [31:0] cpu_mem_la_addr;
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logic [31:0] cpu_mem_la_wdata;
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logic [ 3:0] cpu_mem_la_wstrb;
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/* verilator lint_on UNUSED */
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// PicoRV32 // Defaults
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picorv32 #(.ENABLE_COUNTERS(0), // = 1,
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.ENABLE_COUNTERS64(0), // = 1,
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.ENABLE_REGS_16_31(1), // = 1,
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.ENABLE_REGS_DUALPORT(1), // = 1,
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.LATCHED_MEM_RDATA(0), // = 0,
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.TWO_STAGE_SHIFT(1), // = 1,
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.BARREL_SHIFTER(0), // = 0,
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.TWO_CYCLE_COMPARE(0), // = 0,
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.TWO_CYCLE_ALU(0), // = 0,
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.COMPRESSED_ISA(0), // = 0,
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.CATCH_MISALIGN(1), // = 1,
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.CATCH_ILLINSN(1), // = 1,
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.ENABLE_PCPI(0), // = 0,
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.ENABLE_MUL(0), // = 0,
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.ENABLE_FAST_MUL(0), // = 0,
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.ENABLE_DIV(0), // = 0,
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.ENABLE_IRQ(0), // = 0,
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.ENABLE_IRQ_QREGS(0), // = 1,
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.ENABLE_IRQ_TIMER(0), // = 1,
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.ENABLE_TRACE(0), // = 0,
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.REGS_INIT_ZERO(0), // = 0,
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.MASKED_IRQ(32'h 0000_0000), // = 32'h 0000_0000,
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.LATCHED_IRQ(32'h ffff_ffff), // = 32'h ffff_ffff,
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.PROGADDR_RESET(32'h 0000_0000), // = 32'h 0000_0000,
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.PROGADDR_IRQ(32'h 0000_0010), // = 32'h 0000_0010,
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.STACKADDR(32'h ffff_ffff)) // = 32'h ffff_ffff
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picorv32
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(.clk(clock),
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.resetn(~reset),
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.mem_valid(cpu_mem_valid), // output reg
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.mem_instr(cpu_mem_instr), // output reg
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.mem_ready(cpu_mem_ready), // input
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.mem_addr(cpu_mem_addr), // output reg [31:0]
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.mem_wdata(cpu_mem_wdata), // output reg [31:0]
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.mem_wstrb(cpu_mem_wstrb), // output reg [ 3:0]
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.mem_rdata(cpu_mem_rdata), // input [31:0]
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// Look-Ahead Interface
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.mem_la_read(cpu_mem_la_read), // output
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.mem_la_write(cpu_mem_la_write), // output
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.mem_la_addr(cpu_mem_la_addr), // output [31:0]
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.mem_la_wdata(cpu_mem_la_wdata), // output reg [31:0]
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.mem_la_wstrb(cpu_mem_la_wstrb), // output reg [ 3:0]
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// Unused
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/* verilator lint_off PINCONNECTEMPTY */
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.pcpi_valid(), // output reg
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.pcpi_insn(), // output reg [31:0]
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.pcpi_rs1(), // output [31:0]
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.pcpi_rs2(), // output [31:0]
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.pcpi_wr(1'b0), // input
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.pcpi_rd(32'd0), // input [31:0]
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.pcpi_wait(1'b0), // input
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.pcpi_ready(1'b0), // input
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.irq(32'd0), // input [31:0]
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.eoi(), // output reg [31:0]
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.trap(), // output reg
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.trace_valid(), // output reg
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.trace_data() // output reg [35:0]
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/* verilator lint_on PINCONNECTEMPTY */
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);
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// -- Bus multiplexer
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// Slaves address ranges:
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// 0 - 0x00000000-0x0000ffff
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// 1 - 0x00010000-0x0001ffff
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// 2 - 0x01000000-0x01000fff
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// i_slave_rdata bits:
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// 0: i_slave_rdata[31:0]
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// 1: i_slave_rdata[63:32]
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// 2: i_slave_rdata[95:64]
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logic [31:0] rdata_ram;
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logic [31:0] rdata_rom;
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logic [31:0] rdata_reg;
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logic valid_ram;
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logic ready_ram;
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logic valid_rom;
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logic ready_rom;
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logic valid_reg;
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logic ready_reg;
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bus_mux bus_mux
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(.clock, .reset,
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// CPU
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.i_la_addr(cpu_mem_la_addr),
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.o_rdata(cpu_mem_rdata),
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.i_valid(cpu_mem_valid),
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.o_ready(cpu_mem_ready),
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// Slaves
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.i_slave_rdata({rdata_reg, rdata_rom, rdata_ram}),
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.o_slave_valid({valid_reg, valid_rom, valid_ram}),
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.i_slave_ready({ready_reg, ready_rom, ready_ram}));
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// -- CPU memory
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picorv32_tcm #(.ADDR_WIDTH(MEM_ADDR_WIDTH),
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.USE_LOOK_AHEAD(1),
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.USE_ADDR_MUX(0),
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.MEM_INIT_FILE("../source/firmware/fw.mem"))
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main_tcm
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(.clock, .reset,
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/* PicoRV32 bus interface */
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.mem_valid(valid_ram),
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.mem_ready(ready_ram),
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.mem_addr(cpu_mem_addr[MEM_ADDR_WIDTH-1:0]),
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.mem_wdata(cpu_mem_wdata),
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.mem_wstrb(cpu_mem_wstrb),
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.mem_rdata(rdata_ram),
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.mem_la_addr(cpu_mem_la_addr[MEM_ADDR_WIDTH-1:0]));
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// -- DATA memory
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picorv32_tcm #(.ADDR_WIDTH(ROM_ADDR_WIDTH),
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.USE_LOOK_AHEAD(1),
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.USE_ADDR_MUX(0))
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rom
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(.clock, .reset,
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/* PicoRV32 bus interface */
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.mem_valid(valid_rom),
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.mem_ready(ready_rom),
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.mem_addr(cpu_mem_addr[MEM_ADDR_WIDTH-1:0]),
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.mem_wdata(cpu_mem_wdata),
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.mem_wstrb(cpu_mem_wstrb),
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.mem_rdata(rdata_rom),
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.mem_la_addr(cpu_mem_la_addr[MEM_ADDR_WIDTH-1:0]));
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// -- Registers
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logic ctrl_stop;
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logic [31:0] md5_out0;
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logic [31:0] md5_out1;
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logic [31:0] md5_out2;
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logic [31:0] md5_out3;
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logic [7:0] i_console_data;
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logic [7:0] o_console_data;
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logic console_send;
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logic reg_write;
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logic reg_read;
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assign ready_reg = 1'b1;
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assign reg_write = valid_reg & |(cpu_mem_wdata);
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assign reg_read = valid_reg & &(~cpu_mem_wdata);
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assign i_console_data = 8'ha5;
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assign done = ctrl_stop;
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assign md5 = {md5_out3, md5_out2, md5_out1, md5_out0};
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io_reg io_reg
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(.clock, .reset,
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// CPU
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.i_addr({16'd0, cpu_mem_addr[15:0]}),
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.i_data(cpu_mem_wdata),
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.o_data(rdata_reg),
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.i_ben(cpu_mem_wstrb),
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.i_write(reg_write),
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.i_read(reg_read),
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// Ctrl
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.o_ctrl_stop(ctrl_stop),
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// MD5
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// .i_md5_data_data(data_in),
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.o_md5_out0_data(md5_out0),
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.o_md5_out1_data(md5_out1),
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.o_md5_out2_data(md5_out2),
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.o_md5_out3_data(md5_out3),
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// Console
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.i_console_data(i_console_data),
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.o_console_data(o_console_data),
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.o_console_send_hsreq(console_send),
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// Unused
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/* verilator lint_off PINCONNECTEMPTY */
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.o_console__rnotify(),
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.i_console_send_hsack(1'b1),
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.i_console_send(1'b0),
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.i_console_valid(1'b1)
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/* verilator lint_on PINCONNECTEMPTY */
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);
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// Print console output
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initial
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forever begin
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@(posedge clock);
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if (!reset && console_send) begin
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$write("%c", o_console_data);
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$fflush;
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end
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end
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endmodule // testbench
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