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Change benchmark to calc MD5 on 1024 softcores

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This commit is contained in:
Nikolay Puzanov
2023-06-15 17:40:46 +03:00
parent 89c82cb611
commit 047bd9c42b
21 changed files with 1376 additions and 931 deletions
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118
source/io_reg.v
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@@ -17,6 +17,18 @@ module io_reg
/* ---- 'ctrl' ---- */
output wire o_ctrl_stop,
/* ---- 'md5_out0' ---- */
output wire [31:0] o_md5_out0_data,
/* ---- 'md5_out1' ---- */
output wire [31:0] o_md5_out1_data,
/* ---- 'md5_out2' ---- */
output wire [31:0] o_md5_out2_data,
/* ---- 'md5_out3' ---- */
output wire [31:0] o_md5_out3_data,
/* ---- 'console' ---- */
output wire o_console__rnotify,
input wire [7:0] i_console_data,
@@ -28,13 +40,39 @@ module io_reg
/* ---- Address decoder ---- */
wire ctrl_select;
wire md5_out0_select;
wire md5_out1_select;
wire md5_out2_select;
wire md5_out3_select;
wire console_select;
assign ctrl_select =
i_addr[2] == 1'b0;
i_addr[2] == 1'b0 &&
i_addr[3] == 1'b0 &&
i_addr[4] == 1'b0;
assign md5_out0_select =
i_addr[2] == 1'b1 &&
i_addr[3] == 1'b0 &&
i_addr[4] == 1'b0;
assign md5_out1_select =
i_addr[2] == 1'b0 &&
i_addr[3] == 1'b1 &&
i_addr[4] == 1'b0;
assign md5_out2_select =
i_addr[2] == 1'b1 &&
i_addr[3] == 1'b1 &&
i_addr[4] == 1'b0;
assign md5_out3_select =
i_addr[2] == 1'b0 &&
i_addr[4] == 1'b1;
assign console_select =
i_addr[2] == 1'b1;
i_addr[2] == 1'b1 &&
i_addr[4] == 1'b1;
/* ---- 'ctrl' ---- */
@@ -50,6 +88,70 @@ module io_reg
end
/* ---- 'md5_out0' ---- */
reg [31:0] md5_out0_data;
assign o_md5_out0_data = md5_out0_data;
always @(posedge clock)
if (reset)
md5_out0_data <= 32'b0;
else
if (md5_out0_select && i_write) begin
if (i_ben[0]) md5_out0_data[7:0] <= i_data[7:0];
if (i_ben[1]) md5_out0_data[15:8] <= i_data[15:8];
if (i_ben[2]) md5_out0_data[23:16] <= i_data[23:16];
if (i_ben[3]) md5_out0_data[31:24] <= i_data[31:24];
end
/* ---- 'md5_out1' ---- */
reg [31:0] md5_out1_data;
assign o_md5_out1_data = md5_out1_data;
always @(posedge clock)
if (reset)
md5_out1_data <= 32'b0;
else
if (md5_out1_select && i_write) begin
if (i_ben[0]) md5_out1_data[7:0] <= i_data[7:0];
if (i_ben[1]) md5_out1_data[15:8] <= i_data[15:8];
if (i_ben[2]) md5_out1_data[23:16] <= i_data[23:16];
if (i_ben[3]) md5_out1_data[31:24] <= i_data[31:24];
end
/* ---- 'md5_out2' ---- */
reg [31:0] md5_out2_data;
assign o_md5_out2_data = md5_out2_data;
always @(posedge clock)
if (reset)
md5_out2_data <= 32'b0;
else
if (md5_out2_select && i_write) begin
if (i_ben[0]) md5_out2_data[7:0] <= i_data[7:0];
if (i_ben[1]) md5_out2_data[15:8] <= i_data[15:8];
if (i_ben[2]) md5_out2_data[23:16] <= i_data[23:16];
if (i_ben[3]) md5_out2_data[31:24] <= i_data[31:24];
end
/* ---- 'md5_out3' ---- */
reg [31:0] md5_out3_data;
assign o_md5_out3_data = md5_out3_data;
always @(posedge clock)
if (reset)
md5_out3_data <= 32'b0;
else
if (md5_out3_select && i_write) begin
if (i_ben[0]) md5_out3_data[7:0] <= i_data[7:0];
if (i_ben[1]) md5_out3_data[15:8] <= i_data[15:8];
if (i_ben[2]) md5_out3_data[23:16] <= i_data[23:16];
if (i_ben[3]) md5_out3_data[31:24] <= i_data[31:24];
end
/* ---- 'console' ---- */
reg [7:0] console_data;
assign o_console_data = console_data;
@@ -77,14 +179,26 @@ module io_reg
/* ---- Read multiplexer ---- */
reg [31:0] data_ctrl;
reg [31:0] data_md5_out0;
reg [31:0] data_md5_out1;
reg [31:0] data_md5_out2;
reg [31:0] data_md5_out3;
reg [31:0] data_console;
assign o_data =
data_ctrl |
data_md5_out0 |
data_md5_out1 |
data_md5_out2 |
data_md5_out3 |
data_console;
always @(*) begin
data_ctrl = 32'd0;
data_md5_out0 = 32'd0;
data_md5_out1 = 32'd0;
data_md5_out2 = 32'd0;
data_md5_out3 = 32'd0;
data_console = 32'd0;
if (console_select) begin