Change benchmark to calc MD5 on 1024 softcores

source/bus_mux.v

@@ -2,11 +2,13 @@
 
 // Slaves address ranges:
 //   0 - 0x00000000-0x0000ffff
-//   1 - 0x01000000-0x01000fff
+//   1 - 0x00010000-0x0001ffff
+//   2 - 0x01000000-0x01000fff
 
 // i_slave_rdata bits:
 //   0: i_slave_rdata[31:0]
 //   1: i_slave_rdata[63:32]
+//   2: i_slave_rdata[95:64]
 
 module bus_mux
   (input wire clock,
@@ -23,32 +25,38 @@ module bus_mux
    output wire o_ready,
 
    // Slaves interface
-   input wire [63:0] i_slave_rdata,
-   output wire [1:0] o_slave_valid,
-   input wire [1:0] i_slave_ready);
+   input wire [95:0] i_slave_rdata,
+   output wire [2:0] o_slave_valid,
+   input wire [2:0] i_slave_ready);
 
-  wire [1:0] selector;
-  reg [1:0] selector_reg;
+  wire [2:0] selector;
+  reg [2:0] selector_reg;
 
   always @(posedge clock)
     if (reset)
-      selector_reg <= 2'd0;
+      selector_reg <= 3'd0;
     else
       if (!i_valid)
         selector_reg <= selector;
 
   assign selector[0] =
+    i_la_addr[16] == 1'b0 &&
     i_la_addr[24] == 1'b0;
 
   assign selector[1] =
+    i_la_addr[16] == 1'b1 &&
+    i_la_addr[24] == 1'b0;
+
+  assign selector[2] =
     i_la_addr[24] == 1'b1;
 
-  assign o_slave_valid = selector_reg & {2{i_valid}};
+  assign o_slave_valid = selector_reg & {3{i_valid}};
   assign o_ready = |(i_slave_ready & selector_reg);
 
   assign o_rdata =
     (i_slave_rdata[31:0] & {32{selector_reg[0]}}) |
-    (i_slave_rdata[63:32] & {32{selector_reg[1]}});
+    (i_slave_rdata[63:32] & {32{selector_reg[1]}}) |
+    (i_slave_rdata[95:64] & {32{selector_reg[2]}});
 
 `ifdef FORMAL
 
@@ -57,7 +65,7 @@ module bus_mux
     ones = 0;
 
     // Check for selector is zero or one-hot value
-    for (n = 0; n < 2; n = n + 1)
+    for (n = 0; n < 3; n = n + 1)
       if (selector[n] == 1'b1)
         ones = ones + 1;
 
@@ -66,27 +74,34 @@ module bus_mux
     // Check for correct address ranges decode
     if (i_la_addr >= 32'h0 && i_la_addr <= 32'hffff)
       assert(selector[0] == 1'b1);
-    if (i_la_addr >= 32'h1000000 && i_la_addr <= 32'h1000fff)
+    if (i_la_addr >= 32'h10000 && i_la_addr <= 32'h1ffff)
       assert(selector[1] == 1'b1);
+    if (i_la_addr >= 32'h1000000 && i_la_addr <= 32'h1000fff)
+      assert(selector[2] == 1'b1);
   end
 
   // Check multiplexer
   always @(*) begin : formal_mux
     case (selector_reg)
-      2'b01: begin
+      3'b001: begin
         assert(o_rdata == i_slave_rdata[31:0]);
         assert(o_ready == i_slave_ready[0]);
         assert(o_slave_valid[0] == i_valid);
       end
-      2'b10: begin
+      3'b010: begin
         assert(o_rdata == i_slave_rdata[63:32]);
         assert(o_ready == i_slave_ready[1]);
         assert(o_slave_valid[1] == i_valid);
       end
-      2'b00: begin
+      3'b100: begin
+        assert(o_rdata == i_slave_rdata[95:64]);
+        assert(o_ready == i_slave_ready[2]);
+        assert(o_slave_valid[2] == i_valid);
+      end
+      3'b000: begin
         assert(o_rdata == 32'd0);
         assert(o_ready == 1'b0);
-        assert(o_slave_valid == 2'd0);
+        assert(o_slave_valid == 3'd0);
       end
     endcase
   end