8 lines
184 B
Systemverilog
8 lines
184 B
Systemverilog
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`timescale 1ps/1ps
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module top #(parameter CPU_COUNT = 1024);
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logic clock = 1'b0;
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initial forever #5000 clock = ~clock;
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testbench #(CPU_COUNT) testbench (clock);
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endmodule
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