simbench/test-cvc/testbench.patch

diff --git a/source/testbench.sv b/source/testbench.sv
index 2949591..084d7a3 100644
--- a/source/testbench.sv
+++ b/source/testbench.sv
@@ -34,7 +34,7 @@ module testbench #(parameter CPU_COUNT = 1024)
             data_len = DATA_LEN;
 
         int reset_duration;
-        initial reset_duration = $urandom % CPU_COUNT + 2;
+        initial reset_duration = $unsigned($random) % CPU_COUNT + 2;
         assign reset = cycle <= reset_duration;
 
         always @(posedge clock) begin