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198
hny2026/src/Hny2026.scala
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198
hny2026/src/Hny2026.scala
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package hny2026
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import circt.stage.ChiselStage
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import chisel3._
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import chisel3.util._
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/**
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* Generates a single-cycle strobe pulse at a rate determined by the supplied configuration. The
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* strobe is used to time the transmission of bits from a character to the LED driver in {@link
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* CharSender}.
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*
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* <p>The strobe generator works by counting clock cycles so that a pulse occurs once every
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* <code>cntToInt</code> cycles plus a fractional adjustment. The fractional part is implemented by
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* a second counter that counts <code>fracCntTo</code> pulses before a full <code>cntToInt</code>
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* cycle is considered complete. This yields a frame rate accurate to within {@code
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* frameRateAccuracy}.</p>
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*
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* @param cfg configuration that contains the clock frequency, frame rate and accuracy target.
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*/
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class StrobeGenerator(cfg: HnyConfig) extends Module {
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val strobe = IO(Output(Bool()))
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val cntTo = (((cfg.clockFreq / cfg.frameRate) / cfg.frameRateAccuracy).round * cfg.frameRateAccuracy)
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val cntToInt = cntTo.round
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val cntInt = RegInit(0.U(log2Up(cntToInt+1).W))
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val cntIntDone = cntInt === 0.U
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val fracPart = cntTo - cntToInt
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val cntFracDone = Wire(Bool())
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strobe := cntIntDone
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if (fracPart != 0) {
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val fracCntTo = (1 / fracPart.abs).toInt
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val fracCnt = RegInit(0.U(log2Up(fracCntTo).W))
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when(cntIntDone) {
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when(cntFracDone) {
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fracCnt := 0.U
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} otherwise {
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fracCnt := fracCnt + 1.U
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}
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}
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cntFracDone := fracCnt === (fracCntTo-1).U
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} else {
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cntFracDone := false.B
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}
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when(cntIntDone) {
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when(cntFracDone) {
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cntInt := {
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if (fracPart > 0)
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cntToInt.U
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else
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(cntToInt - 2).U
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}
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} otherwise {
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cntInt := (cntToInt - 1).U
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}
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} otherwise {
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cntInt := cntInt - 1.U
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}
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}
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/**
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* Convenience constructor for a strobe generator.
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*
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* @param cfg configuration for the strobe generator.
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* @return a {@code Bool} that goes high for one cycle at the desired frame rate.
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*/
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object StrobeGenerator {
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def apply(cfg: HnyConfig): Bool = {
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val sg = Module(new StrobeGenerator(cfg))
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sg.strobe
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}
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}
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/**
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* Sends a single byte of data to the LED matrix. The module implements a 1-bit wide serial output
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* using the two signals {@code one} and {@code zero}. When the {@code strobe} from {@link
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* StrobeGenerator} goes high, the next bit of the current character is shifted out. The MSB is a
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* parity bit that is the XOR of all data bits. The last bit is a flag that indicates
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* that the character has been fully transmitted.
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*
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* @param cfg configuration that defines the data width and other timing parameters.
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*/
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class CharSender(cfg: HnyConfig) extends Module {
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val io = IO(new Bundle {
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val data = Flipped(Decoupled(UInt(cfg.dataWidth.W)))
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val one = Bool()
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val zero = Bool()
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})
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val strobe = StrobeGenerator(cfg)
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val send = RegInit(false.B)
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val data = Reg(Bits((cfg.dataWidth+2).W)) // Extra bits for parity and done flag
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val one = RegInit(false.B)
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val zero = RegInit(false.B)
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val parity = io.data.bits.xorR
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io.data.ready := !send
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io.one := one
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io.zero := zero
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when(send) {
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when(strobe) {
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data := data >> 1
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when(data.head(data.getWidth-1) === 0.U) {
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send := false.B
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} otherwise {
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one := data(0)
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zero := ~data(0)
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}
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}
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} otherwise {
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one := false.B
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zero := false.B
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when(io.data.valid) {
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data := true.B ## parity ## io.data.bits
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send := true.B
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}
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}
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}
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/**
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* Top-level module that drives the RGB LEDs to display a string. Each character of the provided
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* string is sent to the LED driver one after the other. The module uses a {@link CharSender}
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* instance for the actual bit-streaming and routes the {@code one} and {@code zero} signals to the
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* red and green LEDs respectively.
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*
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* @param cfg configuration that controls the serial timing and data width.
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* @param str string to display on the LED matrix.
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*/
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class HNY2026(cfg: HnyConfig, str: String) extends Module {
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val io = IO(new Bundle {
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val ledR = Output(Bool())
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val ledG = Output(Bool())
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val ledB = Output(Bool())
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})
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val sender = Module(new CharSender(cfg))
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val chars = VecInit(str.map(c => c.toByte.U(cfg.dataWidth.W)))
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val charCnt = RegInit(UInt(log2Up(str.length()).W), 0.U)
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sender.io.data.valid := true.B
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sender.io.data.bits := chars(charCnt)
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when(sender.io.data.ready) {
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when(charCnt === (chars.length - 1).U) {
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charCnt := 0.U
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} otherwise {
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charCnt := charCnt + 1.U
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}
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}
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io.ledR := sender.io.one
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io.ledG := sender.io.zero
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io.ledB := false.B
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}
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/**
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* Entry point that parses command-line arguments, creates a {@link HnyConfig} instance and emits
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* the corresponding SystemVerilog file for the {@link HNY2026} module.
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*
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* <pre>
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* mill hny2026.runMain hny2026.HNY2026
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* </pre>
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*
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* Available arguments:
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* <ul>
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* <li><b>clockFreq</b> – clock frequency in Hz (default 27 MHz)</li>
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* </ul>
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*/
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object HNY2026 extends App {
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val argsMap = args.map { s =>
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val ss = s.split("=")
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if (ss.length == 1)
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(ss(0), "")
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else
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(ss(0), ss(1))
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}.toMap
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val clockFreq = argsMap.getOrElse("clockFreq", "27000000").toInt
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println(s"Clock frequency = $clockFreq Hz")
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val cfg = HnyConfig(
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clockFreq = clockFreq,
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frameRate = 30,
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frameRateAccuracy = 0.0001,
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dataWidth = 8
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)
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ChiselStage.emitSystemVerilogFile(
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new HNY2026(cfg, "HNY2026! Vsem dobra :)")
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)
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}
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