Add UTEST_TESTBENCH predefined macro

2022-09-13 15:52:01 +03:00
parent 79f9ac5ad6
commit 9b629cd073
2 changed files with 3 additions and 1 deletions
--- a/utest.scm
+++ b/utest.scm
@@ -649,7 +649,8 @@
 ;;;
 (define (utest-verilog-defines)
  (append
-   `((UTEST_BASE_DIR ,(format "'\"~a\"'" (utest/base-path)))
+   `(UTEST_TESTBENCH
+     (UTEST_BASE_DIR ,(format "'\"~a\"'" (utest/base-path)))
     (UTEST_WORK_DIR ,(format "'\"~a\"'" (utest/work-path))))

   (fold (lambda (x l)